1. Field of the Invention
This invention relates to a magnetic bubble domain chip and more particularly to a chip organization utilizing a unique annihilator-type input/output decoder as well as a unique arrangement of components to permit alternate bit operation.
2. Description of the Prior Art
In the prior art, bubble domains are produced by suitable generators. Typically, in a information storage application, each storage register is associated with a separate generator. Conventional bubble generators, such as current loop generators, require relatively large currents to nucleate bubbles. Therefore, it is highly desirable to reduce the number of generators in a bubble domain chip organization.
The on-chip decoding organization approach has been found to enjoy an advantage of faster access time over other systems such as the serial or major-minor loop organization. The slower access time of known systems is normally attributed to designs that require all blocks of information to be arranged in series, thus, requiring the blocks to be rotated, in sequence, to the input/output port. The known systems generally also require read data to be recycled back into the minor loops which lengthens and further complicates the read operation.
In known decoder organizations, all blocks of information are arranged in parallel whereby longer access time and discontinuous data readout can be substantially overcome. However, in the past, the requirement of decoder lines including switches and passive annihilators in the chip designs have been plagued with small margin overlap of the decoder switches and other circuit components. This problem substantially reduces the effectiveness of the existing decoder organization schemes. In addition, the prior art chip organizations require a large number of decoder components and the attendant large driving power. Moreover, these decoder components require separate control leads which makes the chip organization very complicated.
With respect to prior art chip organizations, reference is made to G. S. Almasi et al., "Fabrication and Operation of a Self-Contained Bubble Memory Chip", AIP Conference Proc., No. 5, pp. 220-224, 1972; H. Chang et al., "Self-Contained Magnetic Bubble Domain Memory Chip", IEEE Transactions Magnetics, Vol. MAG-8, No. 2, pp. 214-222, 1972; Chang et al., U.S. Pat. No. 3,701,125 or Chang et al., U.S. Pat. No. 3,689,902.
Reference is also made to the copending U.S. patent application bearing Ser. No. 614,401 entitled BUBBLE DOMAIN CIRCUIT ORGANIZATION by T. T. Chen, filed Sept. 18, 1975 and now U.S. Pat. No. 4,032,905, and Ser. No. 633,306 entitled CONSECUTIVE BIT ACCESS OF MAGNETIC BUBBLE DOMAIN MEMORY DEVICES by I. S. Gergis, filed Nov. 19, 1975, each of which is assigned to the common assignee.
The Ser. No. 614,401 application (Chen) teaches an on-chip bubble domain circuit organization having a unique multiple output replicator and decoder arrangement. This arrangement permits operates in a dual phase and double polarity mode, (i.e. positive and negative pulses at different phasing). This arrangement requires relatively tight control on operating conditions such as pulse amplitude and phasing. Modification to the decoder arrangement permit wider operaging margins but require more decoder stages and, thus, decoder lines, with the attendant problems of complexity.
The Ser. No. 633,306 application (Gergis) teaches a dual channel concept with alternate bit propagation in the input/output sections but not in the storage areas. This latter arrangement provides wider operating margins for the chip organizaton.